请教ABB TDM光通信的VERILOG实现。

谭力源 · 发表于 2016-5-20 23:56:22

我是个新手。由于工程需要，在FPGA上实现ABB TDM光通信的串并协议转换。请教各位前辈该如何设计改程序呢？

ABB TDM通信协议 (原文件名:2011-10-12 10 48 02.jpg)
自己写了一个程序，出现错误如下：“The logic for ** does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.”。我的程序如下:

module TDM32(clk,fstart,din,dout,rdy);

input clk;
input fstart;
input din;
output [31:0] dout;
output rdy;

reg [31:0] dout;
reg rdy;
reg [31:0] data_temp;
reg [32:0] counter;
reg en;

initial begin
      counter<=32;
      en<=0;
      data_temp<=0;
end

always @(negedge fstart or posedge clk) begin
      if(counter==32)begin
            en<=1;
            rdy<=0;
            data_temp<=0;
      end
      else if(counter>0 && counter<=31)begin
            data_temp<=(data_temp<<1);
            data_temp[0]<=din;
      end
      else if(counter==0)begin
            en<=0;
            dout<=data_temp;
            counter<=32;
            rdy<=1;
      end
      else begin
            en<=0;
            data_temp<=0;
            counter<=32;
            rdy<=0;
      end
end

endmodule