clk_wiz_0 thepll (// Clock in ports
.clk_in1(clk_50m), // Clock out ports
.clk_out1(clk_20m), // Status and control signals
.reset(),
.locked(pll_lock)
);
counter #(.WIDTH(25)) gcnt1 (.clock(clk_20m),.reset(reset),.en(1),.cnt_out(the_cnt));
endmodule
然后自己写了个计数器也加进来
module counter
#(parameter WIDTH=16)
(
input clock,reset,en,
output wire [WIDTH-1:0] cnt_out
);
reg [WIDTH-1:0] count;
// Reset if needed, or increment if counting is enabled
assign cnt_out = count;
always @ (posedge clock or posedge reset)
begin
if (reset)
count<=0;
else if(en)
count <= count + 1;
end
endmodule