标题: Verilog一道小题，有点意思 [打印本页] 作者: 我爱因仑风 时间: 2016-5-31 19:11 标题: Verilog一道小题，有点意思 适合我这样的新手
题目：
The example below models a flip-flop with asynchronous set/reset logic (active low).
The model synthesizes correctly, but there is a corner case where simulation results are incorrect.
What is the corner case?
always_ff @( posedge clk
or negedge rst_n // active-low reset
or negedge set_n // active-low set
)
if (!rst_n) // reset has priority over set
q_out <= ’0; // reset all bits to zero
else if (!set_n)
q_out <= ’1; // set all bits to one
else
q_out <= data_in; // d input assignment