(原文件名:图片 001.jpg)
module LCD(clk, rs, rw, en,dat);
input clk;
output [7:0] dat;
output rs,rw,en;
//tri en;
reg e;
reg [7:0] dat;
reg rs;
reg [15:0] counter;
reg [3:0] current,next;
reg clkr;
reg [1:0] cnt;
parameter set0=4'h0;
parameter set1=4'h1;
parameter set2=4'h2;
parameter set3=4'h3;
parameter dat0=4'h4;
parameter dat1=4'h5;
parameter dat2=4'h6;
parameter dat3=4'h7;
parameter dat4=4'h8;
parameter dat5=4'h9;
parameter nul=4'ha;
always @(posedge clk) //da de shi zhong pinlv
begin
counter=counter+1;
if(counter==16'h000f)
clkr=~clkr;
end
always @(posedge clkr)
begin
current=next;
case(current)
set0: begin rs<=0; dat<=8'h30; next<=set1; end
set1: begin rs<=0; dat<=8'h0c; next<=set2; end
set2: begin rs<=0; dat<=8'h6; next<=set3; end
set3: begin rs<=0; dat<=8'h1; next<=dat0; end
dat0: begin rs<=1; dat<=8'hb0; next<=dat1; end
dat1: begin rs<=1; dat<=8'ha1; next<=dat2; end
dat2: begin rs<=1; dat<="F"; next<=dat3; end
dat3: begin rs<=1; dat<="
"; next<=dat4; enddat4: begin rs<=1; dat<="G"; next<=dat5; end
dat5: begin rs<=1; dat<="A"; next<=nul; end
nul: begin rs<=0; dat<=8'h00; //这段保证前段显示部分至少执行一遍 然后 把液晶的E 脚 拉高
if(cnt!=2'h2)
begin
e<=0;next<=set0;cnt<=cnt+1;
end
else
begin next<=nul; e<=1;
end
end
default: next=set0;
endcase
end
assign en=clkr|e;
assign rw=0;
endmodule
我在网上找了很久没有发现有价值的东西，所以自己花了点时间写了一个 很简单
献给大家 多提意见共同进步
不只为什么 最后的控制en输出的时候与门不行，后来换成或门可以了
点击此处下载 ourdev_382757.rar(文件大小:195K) (原文件名
CD.rar)