library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shumaguan is
port(
clk:in std_logic;
weiut std_logic_vector(7 downto 0);
duanut std_logic_vector(6 downto 0)
);
end entity shumaguan;
architecture shumaguan of shumaguan is
signal wei0:std_logic_vector(7 downto 0) := "01111111";
signal duan0:std_logic_vector(3 downto 0) := "0000";
begin
clk0:process(clk)
begin
wei <= "00000000"; --位选,低电平有效
end process clk0;
clk1:process(clk)
begin
duan <= "0100100"; --段选,顺序是GFEDCBA,不含小数点
end process clk1;
end architecture shumaguan;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shumaguan is
port(
clk:in std_logic;
weiut std_logic_vector(7 downto 0);
duanut std_logic_vector(6 downto 0)
);
end entity shumaguan;
architecture shumaguan of shumaguan is
signal wei0:std_logic_vector(7 downto 0) := "01111111";
signal duan0:std_logic_vector(3 downto 0) := "0000";
begin
clk0:process(clk)
begin
if (wei0="01111111") then
wei0 <= "10111111";
elsif (wei0="10111111") then
wei0 <= "11011111";
elsif (wei0="11011111") then
wei0 <= "11101111";
elsif wei0="11101111" then
wei0 <= "11110111";
elsif wei0="11110111" then
wei0 <= "11111011";
elsif wei0="11111011" then
wei0 <= "11111101";
elsif wei0="11111101" then
wei0 <= "11111110";
else
wei0 <= "01111111";
end if;
wei <= wei0;
end process clk0;
clk1:process(clk)
begin
duan0 <= "0010";
if duan0="0000" then
duan <= "1000000";
elsif duan0="0001" then
duan <= "1111001";
elsif duan0="0010" then
duan <= "0100100";
elsif duan0="0011" then
duan <= "0110000";
elsif duan0="0100" then
duan <= "0011001";
elsif duan0="0101" then
duan <= "0010010";
elsif duan0="0110" then
duan <= "0000010";
elsif duan0="0111" then
duan <= "1011000";
elsif duan0="1000" then
duan <= "0000000";
elsif duan0="1001" then
duan <= "0010000";
else
duan <= "1000000";
end if;
end process clk1;
end architecture shumaguan;